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ADSP-BF531 / ADSP-BF532 / ADSP-BF533
Capacitive Loading
16
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 47 ). V LOAD is 0.95 V for V DDEXT
(nominal) = 1.8 V or 1.5 V for V DDEXT (nominal) =
2.5 V/3.3 V. Figure 48 through Figure 59 on Page 48 show how
output rise time varies with capacitance. The delay and hold
specifications given should be derated by a factor derived from
these figures. The graphs in these figures may not be linear out-
side the ranges shown.
14
12
10
8
6
RISE TIME
FALL TIME
4
TESTER PIN ELECTRONICS
2
50 Ω
V LOAD
T1
DUT
0
0
50
100 150
200
250
70 Ω
50 Ω
45 Ω
ZO = 50 Ω (impedance)
TD = 4.04 ± 1.18 ns
OUTPUT
LOAD CAPACITANCE (pF)
Figure 48. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at V DDEXT = 1.75 V
4pF
2pF
0.5pF
14
400 Ω
12
RISE TIME
10
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
Figure 47. Equivalent Device Loading for AC Measurements
8
6
4
2
FALL TIME
(Includes All Fixtures)
0
0
50
100 150
200
250
LOAD CAPACITANCE (pF)
Figure 49. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at V DDEXT = 2.25 V
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100 150
200
250
LOAD CAPACITANCE (pF)
Figure 50. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at V DDEXT = 3.65 V
Rev. I
|
Page 46 of 64 |
August 2013
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ADZS-BF537-STAMP
制造商:Analog Devices 功能描述:Microcontroller Development Tool
ADZS-BF538-EZLITE
制造商:Analog Devices 功能描述:- Bulk
ADZSBF538FEZLITE
制造商:Analog Devices 功能描述:RES Wirewound 6927 75Ohm 1% 3W 20PPM SMD T/R